For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
The operation of spin torque devices is based on the phenomenon of spin transfer torque. If a current is passed through a magnetization layer, called the fixed magnetic layer, it will come out spin polarized. With the passing of each electron, its spin (which is angular momentum of the electron) will be added to the magnetization in a next magnetic layer, called the free magnetic layer, and will cause its small change. This is, in effect, a torque-causing precession of magnetization. Due to reflection of electrons, a torque is also exerted on the magnetization of an associated fixed magnetic layer. In the end, if the current exceeds a certain critical value (given by damping caused by the magnetic material and its environment), the magnetization of the free magnetic layer will be switched by a pulse of current, typically in about 1 nanosecond. Magnetization of the fixed magnetic layer may remain unchanged since an associated current is below its threshold due to geometry or due to an adjacent anti-ferromagnetic layer.
However, significant improvements are still needed in the speed and energy required for switching of magnetization. Herein is described such improvements by way of precessionally switched magnetic logic devices and architectures.